![]() The objective is to approximately digitize x to an accuracy of 1/2 n. Mathematically, let V in = xV ref, so x in is the normalized input voltage. The resulting code is the digital approximation of the sampled input voltage and is finally output by the SAR at the end of the conversion (EOC). Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. ![]() ![]() If this analog voltage exceeds V in, then the comparator causes the SAR to reset this bit otherwise, the bit is left as 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code ( V ref/2) into the comparator circuit for comparison with the sampled input voltage. The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. Animation of a 4-bit successive-approximation ADC
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